LL OPAMP Constants ¶

OPAMP power mode ¶

group OPAMP_LL_EC_POWERMODE

Defines

LL_OPAMP_POWER_MODE_NORMAL (0x00000000U) ¶: OPAMP power mode: normal-power

OPAMP speed mode ¶

group OPAMP_LL_EC_SPEEDMODE

Defines

LL_OPAMP_SPEED_MODE_NORMAL (0x00000000U) ¶: OPAMP speed mode: normal-speed

LL_OPAMP_SPEED_MODE_HIGH (OPAMP_CSR_OPAHSM) ¶: OPAMP speed mode: high-speed

OPAMP mode calibration or functional. ¶

group OPAMP_LL_EC_MODE

Defines

LL_OPAMP_MODE_FUNCTIONAL (0x00000000U) ¶: OPAMP functional mode

LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) ¶: OPAMP calibration mode

OPAMP functional mode ¶

group OPAMP_LL_EC_FUNCTIONAL_MODE

Defines

LL_OPAMP_MODE_STANDALONE (0x00000000U) ¶: OPAMP functional mode, OPAMP operation in standalone

LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VM_SEL_1 | OPAMP_CSR_VM_SEL_0) ¶: OPAMP functional mode, OPAMP operation in follower

LL_OPAMP_MODE_PGA (OPAMP_CSR_VM_SEL_1) ¶: OPAMP functional mode, OPAMP operation in PGA

OPAMP PGA external connection mode ¶

group OPAMP_LL_EC_PGA_EXT

Defines

LL_OPAMP_PGA_EXT_NONE (0x00000000U) ¶

In PGA mode, the inverting input is connected to the internal feedback resistor. No external connection on inverting input. Positive gain (Non-Inverting mode)

VINPx: Input signal

LL_OPAMP_PGA_EXT_FILT (OPAMP_CSR_PGA_GAIN_4) ¶

In PGA mode, the inverting input is connected to the internal feedback resistor and to VINM0 for filtering. Positive gain (Non-Inverting mode)

VINPx: Input signal
VINM0 - VOUT: Additional low-pass filtering

LL_OPAMP_PGA_EXT_BIAS (OPAMP_CSR_PGA_GAIN_3) ¶

In PGA mode, the inverting input is connected to the internal feedback resistor. VINM0 is available for bias voltage in non-inverting mode or to use the OPAMP in inverting mode. Negative gain (Inverting mode):

VINPx: Bias voltage
VINM0: Input signal Positive gain (Non-Inverting mode)
VINPx: Input signal
VINM0: Bias voltage

LL_OPAMP_PGA_EXT_BIAS_FILT ( LL_OPAMP_PGA_EXT_BIAS | LL_OPAMP_PGA_EXT_FILT ) ¶

In PGA mode, the inverting input is connected to the internal feedback resistor and to VINM1 for filtering. VINM0 is available for bias voltage in non-inverting mode or to use the OPAMP in inverting mode. Negative gain (Inverting mode):

VINPx: Bias voltage
VINM0: Input signal
VINM1 - VOUT: Additional low-pass filtering Positive gain (Non-Inverting mode)
VINPx: Input signal
VINM0: Bias voltage
VINM1 - VOUT: Additional low-pass filtering

OPAMP PGA gain (relevant when OPAMP is in functional mode PGA) ¶

group OPAMP_LL_EC_MODE_PGA_GAIN

Defines

LL_OPAMP_PGA_GAIN_2 (0x00000000UL) ¶: OPAMP PGA gain 2

LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGA_GAIN_0) ¶: OPAMP PGA gain 4

LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGA_GAIN_1) ¶: OPAMP PGA gain 8

LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGA_GAIN_1 \ | OPAMP_CSR_PGA_GAIN_0) ¶: OPAMP PGA gain 16

LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 ( LL_OPAMP_PGA_GAIN_2 ) ¶: OPAMP PGA gain 2 or -1

LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( LL_OPAMP_PGA_GAIN_4 ) ¶: OPAMP PGA gain 4 or -3

LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( LL_OPAMP_PGA_GAIN_8 ) ¶: OPAMP PGA gain 8 or -7

LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( LL_OPAMP_PGA_GAIN_16 ) ¶: OPAMP PGA gain 16 or -15

OPAMP input non-inverting ¶

group OPAMP_LL_EC_INPUT_NONINVERTING

Defines

LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000U) ¶: OPAMP non-inverting input 0 connected to GPIO (for GPIO mapping, refer to datasheet parameters “OPAMPx_VINP0”)

LL_OPAMP_INPUT_NONINVERT_IO1 (OPAMP_CSR_VP_SEL_0) ¶: OPAMP non-inverting input 1 connected to GPIO (for GPIO mapping, refer to datasheet parameters “OPAMPx_VINP1”)

LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VP_SEL_1) ¶: OPAMP non-inverting input 2 connected to GPIO (for GPIO mapping, refer to datasheet parameters “OPAMPx_VINP2”)

LL_OPAMP_INPUT_NONINVERT_DAC1_CH2 (OPAMP_CSR_VP_SEL) ¶: OPAMP non-inverting input connected to DAC1 channel 2

OPAMP input inverting ¶

group OPAMP_LL_EC_INPUT_INVERTING

Defines

LL_OPAMP_INPUT_INVERT_IO0 (0x00000000U) ¶: OPAMP inverting input connected to GPIO pin. Note: This OPAMP inverting input is used with OPAMP in mode standalone, PGA with external bias or filtering, PGA with inverting gain. In mode PGA, select LL_OPAMP_INPUT_INVERT_INT_PGA and configure input connection, refer to LL_OPAMP_SetPGAExternalMode().

LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VM_SEL_0) ¶: OPAMP inverting input connected to GPIO pin.

LL_OPAMP_INPUT_INVERT_INT_PGA (OPAMP_CSR_VM_SEL_1) ¶

OPAMP inverting input connection depending on PGA mode:

For PGA without external bias or filtering, PGA without inverting gain: inverting input internally connected (not connected to a GPIO pin).
For PGA with external bias or filtering, PGA with inverting gain: inverting input connected to IO0 is used. To configure input connection, refer to LL_OPAMP_SetPGAExternalMode().

LL_OPAMP_INPUT_INVERT_INT_FOLLOWER (OPAMP_CSR_VM_SEL_1 | OPAMP_CSR_VM_SEL_0) ¶: OPAMP inverting input internally connected, intended for OPAMP in mode follower (not connected to a GPIO pin).

OPAMP trimming mode ¶

group OPAMP_LL_EC_TRIMMING_MODE

Defines

LL_OPAMP_TRIMMING_FACTORY (0x00000000U) ¶: OPAMP trimming factors set to factory values

LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) ¶: OPAMP trimming factors set to user values

OPAMP trimming of transistors differential pair NMOS or PMOS ¶

group OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR

Defines

LL_OPAMP_TRIMMING_NMOS (OPAMP_CSR_TRIMOFFSETN \ | OPAMP_CSR_CALSEL) ¶: OPAMP trim for NMOS differential pairs

LL_OPAMP_TRIMMING_PMOS (OPAMP_CSR_TRIMOFFSETP \ | OPAMP_CSR_CALSEL_0) ¶: OPAMP trim for PMOS differential pairs

Definitions of OPAMP hardware constraints delays ¶

group OPAMP_LL_EC_HW_DELAYS

Note

Only OPAMP IP HW delays are defined in OPAMP LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Defines

LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 30U) ¶: Delay for OPAMP startup time

OPAMP Timer-controlled input selection ¶

group OPAMP_LL_EC_TIM_CTRL_INPUT

Note

The switch can be controlled either by a single timer or a combination of them, in this case application has to ‘ORed’ the values below ex LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC6 | LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4

Defines

LL_OPAMP_MUX_INPUT_CTRL_DISABLE (0x00000000UL) ¶: Timer-controlled input selection disabled

LL_OPAMP_MUX_INPUT_CTRL_TIM1_OC6 (OPAMP_TCMR_TIMCM_SEL_0) ¶: Timer-controlled input selection using TIM1 OC6

LL_OPAMP_MUX_INPUT_CTRL_TIM2_OC4 (OPAMP_TCMR_TIMCM_SEL_1) ¶: Timer-controlled input selection using TIM2 OC4

LL_OPAMP_MUX_INPUT_CTRL_TIM12_OC1 (OPAMP_TCMR_TIMCM_SEL_1 \ | OPAMP_TCMR_TIMCM_SEL_0) ¶: Timer-controlled input selection using TIM12 OC1

LL_OPAMP_MUX_INPUT_CTRL_TIM15_OC2 (OPAMP_TCMR_TIMCM_SEL_2) ¶: Timer-controlled input selection using TIM15 OC2

OPAMP Timer-controlled programmable gain ¶

group OPAMP_LL_EC_TIM_CTRL_PGA_GAIN

Defines

LL_OPAMP_MUX_PGA_GAIN_CTRL_DISABLE (0x00000000UL) ¶: Timer-controlled programmable gain selection disabled

LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM1_OC6 (OPAMP_TCMR_TIMPGA_SEL_0) ¶: Timer-controlled programmable gain selection using TIM1 OC6

LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM2_OC4 (OPAMP_TCMR_TIMPGA_SEL_1) ¶: Timer-controlled programmable gain selection using TIM2 OC4

LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM12_OC2 (OPAMP_TCMR_TIMPGA_SEL_1 \ | OPAMP_TCMR_TIMPGA_SEL_0) ¶: Timer-controlled programmable gain selection using TIM12 OC2

LL_OPAMP_MUX_PGA_GAIN_CTRL_TIM15_OC2 (OPAMP_TCMR_TIMPGA_SEL_2) ¶: Timer-controlled programmable gain selection using TIM15 OC2

OPAMP channel output connection ¶

group OPAMP_LL_EC_OUTPUT_CONNECTION

Defines

LL_OPAMP_OUTPUT_CONNECT_EXTERNAL (0x00000000UL) ¶: OPAMP output connected to OPAMP_VOUT pin.

LL_OPAMP_OUTPUT_CONNECT_INTERNAL (OPAMP_CSR_OPAINTOEN) ¶: OPAMP output connected internally to other peripherals (ADC, COMP, …).